搜索资源列表
fpadd
- 利用verilog hdl编写的浮点加法器运算单元,单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
fadd
- it is verilog code for floating point adder
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算,结合vhdl和EPGA可编程技术,完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
fpufiles
- floating point adder mul and sub in verilog code
fpuvhdl_latest
- the code describle a floating point adder with verilog
floating-point-adder
- verilog implementation of the floating point adder
add
- 浮点加法器的用Verilog实现,32位的浮点加法器-Floating point adder Verilog
a-floating-point-adder
- 一个浮点加法器,verilog描述,数据格式:高14位为尾数,低四位位指数(带符号数运算)-A floating point adder Verilog descr iption
float
- 基于Verilog HDL的32位浮点运算加法器的源代码。-Based on the 32-bit floating point adder in Verilog HDL source code.
float
- 32位浮点加法器 verilog语言编写-32-bit floating-point adder verilog language
xjwbwd
- 这个fpadd程序应用verilog语言,实现的功能是简单的浮点加法器。初学的同学们可以一看。-This fpadd program applications verilog language to achieve the function is simple floating point adder. Beginner students can have a look.
fpaddmisc-(1)
- VERILOG CODE FOR FLOating point adder
Float_add
- 该源码利用Verilog HDL语言成功实现了浮点数的加法运算,包括全部工程以及Verilog 源码,经验证,该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful
adder
- 能够实现单精度浮点加法运算。输入引脚有:第一运算数,第二运算数,复位信号,时钟信号。输出信号有:运算结果,运算完成标志。(To achieve a single precision floating-point addition operations)
Fixed-Floating-Point-Adder-Multiplier-master
- Fixed-Floating-Point-Adder-Multiplier with test bench
FP_adder
- 32 bit floating point adder with testbench